The need has recently arisen in advanced processes (gate lengths of 0.35 .mu.m or less), to integrate non-volatile memories of EEPROM type in high-speed devices that use the technique of saliciding of the diffusions. As known, this technique is based on the use of a self-aligned silicide layer (salicide), which reduces the resistivity of the junctions. The salicide layer (typically made of titanium, but also of cobalt or another transition metal) is produced by depositing a titanium layer on the entire surface of the device, and carrying out a heat treatment which makes the titanium react with the silicon, left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the non-reacted titanium (for example deposited on oxide regions) is removed by etching using a suitable solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have a parallel silicide layer with low resistivity (approximately 3-4 .OMEGA./square), which reduces the resistance in series to the transistors. The salicide technique is described for example in the article "Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxidesemi-conductor and complementary metal-oxide-semiconductor technologies", by R. A. Haken, in J. Vac. Sci. Technol. B, vol. 3, No. 6, November/December 1985.
The high voltages necessary for programming non-volatile memories (higher than 16 V) are however incompatible with saliciding the diffusions of memory cells, since the breakdown voltage of salicided junctions is lower than 13 V.
Process flows that allow integration of non-volatile memory cells and high-speed transistors with saliciding have been produced; however, this integration is made difficult by the fact that these components have different characteristics, and require different process steps. The large number of necessary masks is also disadvantageous in these flows.